| Wave Pipelining: Theory and CMOS Implementation 1994 Edition Contributor(s): Gray, C. Thomas (Author), Wentai Liu (Author), Cavin III, Ralph K. (Author) |
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ISBN: 0792393988 ISBN-13: 9780792393986 Publisher: Springer
Binding Type: Hardcover - See All Available Formats & Editions Published: November 1993 Annotation: Wave Pipelining: Theory and CMOS Implementation provides a coherent presentation of the theory of wave pipelined operation of digital circuits and discusses practical design techniques for the realization of wave pipelined circuits in CMOS technology. Wave pipeling is a timing methodology used in digital systems to enhance performance while conserving the number of data registers used. This is achieved by applying new data to the inputs of a combinatorial logic block before the previous outputs are available. In contrast to conventional pipelining, system performance is limited by differences in maximum and minimum circuit delay rather than maximum circuit delays. Realization of practical systems using this technique requires accurate system level and circuit level timing analysis. At the system level, timing constraints identifying valid regions of operation for correct clocking of wave pipelined circuits are presented. Both single stage and multiple stage systems including feedback are considered. At the circuit level, since performance is determined by the maximum circuit delay difference, highly accurate estimates of both maximum and minimum delays are needed. Thus, timing analysis based on traditional gate delay models is not sufficient. For CMOS circuits, data dependent delay models considering the effect of simultaneous multiple input switchings must be used. An algorithm using these delay models for accurate analysis of small to medium sized circuits is implemented in a prototype timing analyzer, XTV. Results are given for a set of benchmark circuits. Click for more in this series: VLSI, Computer Architecture, and Digital Signal Processing |
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| Additional Information |
| BISAC Categories: - Computers | Computer Engineering - Technology & Engineering | Electrical - Computers | Cad-cam |
| Dewey: 621.397 |
| LCCN: 93027386 |
| Series: VLSI, Computer Architecture, and Digital Signal Processing |
| Physical Information: 0.56" H x 6.14" W x 9.21" L (1.10 lbs) 206 pages |
| Features: Bibliography, Illustrated, Index |
| Descriptions, Reviews, Etc. |
| Publisher Description: The quest for higher performance digital systems for applications such as gen- eral purpose computing, signal/image processing, and telecommunications and an increasing cost consciousness have led to a major thrust for high speed VLSI systems implemented in inexpensive and widely available technologies such as CMOS. This monograph, based on the first author's doctoral dissertation, con- centrates on the technique of wave pipelining as one method toward achieving this goal. The primary focus of this monograph is to provide a coherent pre- sentation of the theory of wave pipelined operation of digital circuits and to discuss practical design techniques for the realization of wave pipelined circuits in the CMOS technology. Wave pipelining can be applied to a variety of cir- cuits for increased performance. For example, many architectures that support systolic computation lend themselves to wave pipelined realization. Also, the wave pipeline design methodology emphasizes the role of controlled clock skew in extracting enhanced performance from circuits that are not deeply pipelined. Wave pipelining (also known as maximal rate pipelining) is a timing method- ology used in digital systems to increase the number of effective pipeline stages without increasing the number of physical registers in the pipeline. Using this technique, new data is applied to the inputs of a combinational logic block be- fore the outputs due to previous inputs are available thus effectively pipelining the combinational logic and maximizing the utilization of the logic. |
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