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Fault Tolerant Computer Architecture
Contributor(s): Sorin, Daniel J. (Author)

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 ISBN: 1598299530     ISBN-13: 9781598299533
Publisher: Morgan & Claypool
OUR PRICE: $38.00  

Binding Type: Paperback
Published: June 2009
* Out of Print *

Click for more in this series: Synthesis Lectures on Computer Architecture
Additional Information
BISAC Categories:
- Computers | Systems Architecture - General
Dewey: 004.22
Series: Synthesis Lectures on Computer Architecture
Physical Information: 0.24" H x 7.5" W x 9.25" L (0.47 lbs) 116 pages
 
Descriptions, Reviews, Etc.
Publisher Description:
For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore's law into remarkable increases in performance. Recently, however, the bounty provided by Moore's law has been accompanied by several challenges that have arisen as devices have become smaller, including a decrease in dependability due to physical faults. In this book, we focus on the dependability challenge and the fault tolerance solutions that architects are developing to overcome it. The two main purposes of this book are to explore the key ideas in fault-tolerant computer architecture and to present the current state-of-the-art - over approximately the past 10 years - in academia and industry. Table of Contents: Introduction / Error Detection / Error Recovery / Diagnosis / Self-Repair / The Future
 
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