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Designing Reliable and Efficient Networks on Chips 2009 Edition
Contributor(s): Murali, Srinivasan (Author)

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 ISBN: 1402097565     ISBN-13: 9781402097560
Publisher: Springer
OUR PRICE: $161.49  

Binding Type: Hardcover - See All Available Formats & Editions
Published: April 2009
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Annotation: Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.

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Additional Information
BISAC Categories:
- Technology & Engineering | Electronics - Circuits - General
- Computers | Systems Architecture - General
- Technology & Engineering | Machinery
Dewey: 621.319
LCCN: 2008944292
Series: Lecture Notes in Electrical Engineering
Physical Information: 0.5" H x 6.14" W x 9.21" L (1.05 lbs) 198 pages
Features: Bibliography, Table of Contents
 
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